12-08-2010, 06:47 AM
I am designing a digital divider with and 8 bit number divided by a four bit number. I have a specific question relating to the number of subtractions required.
I could be mistaken, but I believe it takes 5 clock cycles to divide a 8 bit by a four bit number. My question is, if I input a 3 bit number as the divisor into the same divider circuit, would the divisor require a left shift to match up with the 8 bit number and an extra clock cycle to divide the number correctly? Is there an easier way to do it?
You shift both the Dividend and the Divisor so the msb of each number is at the MSB of the 8bit number. You need to count the number of shifts: The counter is decremented with each shift of the dividend, and incremented with each shift of the divisor. I can't remember if you initiate the counter with 0 or 1, but I think it is 0.
This is then the counter you use for the actual division.
I could be mistaken, but I believe it takes 5 clock cycles to divide a 8 bit by a four bit number. My question is, if I input a 3 bit number as the divisor into the same divider circuit, would the divisor require a left shift to match up with the 8 bit number and an extra clock cycle to divide the number correctly? Is there an easier way to do it?
You shift both the Dividend and the Divisor so the msb of each number is at the MSB of the 8bit number. You need to count the number of shifts: The counter is decremented with each shift of the dividend, and incremented with each shift of the divisor. I can't remember if you initiate the counter with 0 or 1, but I think it is 0.
This is then the counter you use for the actual division.
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mileys81:
mileys81: