CS302 Digital Logic Design Solve Quiz 3 Fall 2013

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CS302 Digital Logic Design Solve Quiz 3 Fall 2013


Question # 1 of 10 Total Marks: 1
Bi-stable devices remain in either of their _________ states unless the inputs force the device to switch its state
Select correct option:
Ten
Eight
Three
Two

Question # 2 of 10 Total Marks: 1
____________ is said to occur when multiple internal variables change due to change in one input variable
Select correct option:
Hold and Wait
Clock Skew
Race condition
Hold delay

Question # 3 of 10 Total Marks: 1
A modulus-14 counter has fourteen states requiring_____________
Select correct option:
14 Flip Flops
14 Registers
4 Flip Flops
4 Registers

Question # 4 of 10 Total Marks: 1
The counter states or the range of numbers of a counter is determined by the formula. (“n” represents the total number
of flip-flops)
Select correct option:
(n raise to power 2)
(n raise to power 2 and then minus 1)
(2 raise to power n)
(2 raise to power n and then minus 1)

Question # 5 of 10 Total Marks: 1
In a 4-bit binary counter, the next state after the terminal count in the DOWN mode is ____________
Select correct option:
0000
1111
0001
10000

Question # 6 of 10 Total Marks: 1
Asynchronous mean that_____________
Select correct option:
Each flip-flop after the first one is enabled by the ou
Each flip-flop is enabled by the output of the precedi
Each flip-flop except the last one is enabled by the o
Each alternative flip-flop after the first one is enable

Question # 7 of 10 Total Marks: 1
Three cascaded modulus-10 counters have an overall modulus of
Select correct option:
30
100
1000
10000

Question # 8 of 10 Total Marks: 1
A decade counter can be implemented by truncating the counting sequence of a MOD-20 counter.
Select correct option:
True
False

Question # 9 of 10 Total Marks: 1
The terminal count of a 4-bit binary counter in the DOWN mode is____________
Select correct option:
0000
0011
1100
1111

Question # 10 of 10 Total Marks: 1
the terminal count of a modulus-13 binary counter is
Select correct option:
0000
1111
1101
1100

RCO stands for __________
Select correct option:
Reconfiguration Counter Output
Ripple Counter Output
Reconfiguration Clock Output
Ripple Clock Output

Question # 3 of 10 Total Marks: 1
The glitches due to "Race Condition" can be avoided by using a ___________
Select correct option:
Gated flip-flops
Pulse triggered flip-flops
Positive-Edge triggered flip-flops
Negative-Edge triggered flip-flops

Question # 4 of 10 Total Marks: 1
________ flip-flops are obsolete now.
Select correct option:
Edge-triggered
Master-Slave
T-Flipflop
D-Flipflop

Question # 5 of 10 Total Marks: 1
The minimum time required for the input logic levels to remain stable before the clock transit ion occurs is known as the
___________
Select correct option:
Set-up time
Hold time
Pulse Interval time
Pulse Stability time (PST)

Question # 7 of 10 Total Marks: 1
The Synchronous counters are also known as Ripple Counters:
Select correct option:
True
False

Question # 8 of 10 Total Marks: 1
__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation
delay.
Select correct option:
Race condition
Clock Skew
Ripple Effect
None of given options

Question # 9 of 10 Total Marks: 1
An Astable multivibrator is known as a(n) _______
Select correct option:
Oscillator
Booster
One-shot
Dual-shot

Question # 10 of 10 Total Marks: 1
If a circuit suffers “Clock Skew “ problem, the output of circuit can’t be guarantied.
Select correct option:
True
False

Question # 1 of 10 Total Marks: 1
Design of state diagram is one of many steps used to design
Select correct option:
a clock
a truncated counter
an UP/DOWN counter
any counter

Question # 2 of 10 Total Marks: 1
A synchronous decade counter will have _______ flip-flops
Select correct option:
3
4
7
10

Question # 4 of 10 Total Marks: 1
A mono-stable device only has a single stable state
Select correct option:
True
False

Question # 5 of 10 Total Marks: 1
A one-shot mono-stable device contains _________
Select correct option:
AND gate, Resistor, Capacitor and NOT Gate
NAND gate, Resistor, Capacitor and NOT Gate
NOR gate, Resistor, Capacitor and NOT Gate
XNOR gate, Resistor, Capacitor and NOT Gate

Question # 7 of 10 Total Marks: 1
For a down counter that counts from (111 to 000), if current state is "101" the next state will be _________
Select correct option:
111
110
010
none of given options

Question # 8 of 10 Total Marks: 1
A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flipflop
is
Select correct option:
10 mW
25 mW
64 mW
1024 mW

Question # 9 of 10 Total Marks: 1
The 74HC163 is a 4-bit Synchronous Counter.it has..............data output pins
Select correct option:
2
4
6
8

Question # 2 of 10 Total Marks: 1
Each stage of Master-slave flip-flop works at ____ of the clock signal
Select correct option:
Each stage works on complete clock signal
One fourth
One third
One half
Question # 10 of 10 Total Marks: 1
An Asynchronous Down-counter is implemented (Using J-K flip-flop) by connecting ________
Select correct option:
Q output of all flip-flops to clock input of next flip-flop
Q’ output of all flip-flops to clock input of next flip-flo
Q output of all flip-flops to J input of next flip-flops
Q’ output of all flip-flops to K input of next flip-flops