07-17-2010, 04:50 AM
FINALTERM EXAMINATION
Spring 2009
CS302- Digital Logic Design
Spring 2009
CS302- Digital Logic Design
Question No: 1 ( Marks: 1 ) - Please choose one
The diagram given below represents __________
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► Demorgans law
► Associative law
► Product of sum form
► Sum of product form
Question No: 2 ( Marks: 1 ) - Please choose one
Excess-8 code assigns _______ to “+7”
► 0000
► 1001
► 1000
► 1111
Question No: 3 ( Marks: 1 ) - Please choose one
NOR gate is formed by connecting _________
► OR Gate and then NOT Gate
► NOT Gate and then OR Gate
► AND Gate and then OR Gate
► OR Gate and then AND Gate
Question No: 4 ( Marks: 1 ) - Please choose one
A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout) when A = 1 and B = 1?
►
= 0, Cout = 0
= 0, Cout = 0
► = 0, Cout = 1
► = 1, Cout = 0
► = 1, Cout = 1
Question No: 5 ( Marks: 1 ) - Please choose one
A particular half-adder has
► 2 INPUTS AND 1 OUTPUT
► 2 INPUTS AND 2 OUTPUT
► 3 INPUTS AND 1 OUTPUT
► 3 INPUTS AND 2 OUTPUT
Question No: 6 ( Marks: 1 ) - Please choose one
THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT __________ GATE
► AND
► OR
► NAND
► XOR
Question No: 7 ( Marks: 1 ) - Please choose one
A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY THE MANUFACTURER.
► TRUE
► FALSE
Question No: 8 ( Marks: 1 ) - Please choose one
FLIP FLOPS ARE ALSO CALLED _____________
► BI-STABLE DUALVIBRATORS
► BI-STABLE TRANSFORMER
► BI-STABLE MULTIVIBRATORS
► Bi-stable singlevibrators
Question No: 9 ( Marks: 1 ) - Please choose one
A POSITIVE EDGE-TRIGGERED FLIP-FLOP CHANGES ITS STATE WHEN ________________
► LOW-TO-HIGH TRANSITION OF CLOCK
► HIGH-TO-LOW TRANSITION OF CLOCK
► ENABLE INPUT (EN) IS SET
► PRESET INPUT (PRE) IS SET
Question No: 10 ( Marks: 1 ) - Please choose one
___________ IS ONE OF THE EXAMPLES OF SYNCHRONOUS INPUTS.
► J-K INPUT
► EN INPUT
► Preset input (PRE)
► CLEAR INPUT (CLR)
Question No: 11 ( Marks: 1 ) - Please choose one
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________
► GATED FLIP-FLOPS
► PULSE TRIGGERED FLIP-FLOPS
► POSITIVE-EDGE TRIGGERED FLIP-FLOPS
► NEGATIVE-EDGE TRIGGERED FLIP-FLOPS
Question No: 12 ( Marks: 1 ) - Please choose one
THE DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTERS START FROM _________
► TRUTH TABLE
► K-MAP
► STATE TABLE
► STATE DIAGRAM
Question No: 13 ( Marks: 1 ) - Please choose one
THE HOURS COUNTER IS IMPLEMENTED USING __________
► ONLY A SINGLE MOD-12 COUNTER IS REQUIRED
► MOD-10 AND MOD-6 COUNTERS
► MOD-10 AND MOD-2 COUNTERS
► A SINGLE DECADE COUNTER AND A FLIP-FLOP
Question No: 14 ( Marks: 1 ) - Please choose one
GIVEN THE STATE DIAGRAM OF AN UP/DOWN COUNTER, WE CAN FIND __________
► THE NEXT STATE OF A GIVEN PRESENT STATE
► THE PREVIOUS STATE OF A GIVEN PRESENT STATE
► BOTH THE NEXT AND PREVIOUS STATES OF A GIVEN STATE
► The state diagram shows only the inputs/outputs of a given states
Question No: 15 ( Marks: 1 ) - Please choose one
In ________ outputs depend only on the current state.
► Mealy machine
► MOORE MACHINE
► STATE REDUCTION TABLE
► STATE ASSIGNMENT TABLE
Question No: 16 ( Marks: 1 ) - Please choose one
A SYNCHRONOUS DECADE COUNTER WILL HAVE _______ FLIP-FLOPS
► 3
► 4
► 7
► 10
Question No: 17 ( Marks: 1 ) - Please choose one
A MULTIPLEXER WITH A REGISTER CIRCUIT CONVERTS _________
► SERIAL DATA TO PARALLEL
► PARALLEL DATA TO SERIAL
► Serial data to serial
► PARALLEL DATA TO PARALLEL
Question No: 18 ( Marks: 1 ) - Please choose one
The alternate solution for a multiplexer and a register circuit is _________
► PARALLEL IN / SERIAL OUT SHIFT REGISTER
► SERIAL IN / PARALLEL OUT SHIFT REGISTER
► PARALLEL IN / PARALLEL OUT SHIFT REGISTER
► SERIAL IN / SERIAL OUT SHIFT REGISTER
Question No: 19 ( Marks: 1 ) - Please choose one
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES?
► 2
► 4
► 6
► 8
Question No: 20 ( Marks: 1 ) - Please choose one
A 8-BIT SERIAL IN / PARALLEL OUT SHIFT REGISTER CONTAINS THE VALUE “8”, _____ CLOCK SIGNAL(S) WILL BE REQUIRED TO SHIFT THE VALUE COMPLETELY OUT OF THE REGISTER.
► 1
► 2
► 4
► 8
Question No: 21 ( Marks: 1 ) - Please choose one
5-BIT JOHNSON COUNTER SEQUENCES THROUGH ____ STATES
► 7
► 10
► 32
► 25
Question No: 22 ( Marks: 1 ) - Please choose one
IN ________ Q OUTPUT OF THE LAST FLIP-FLOP OF THE SHIFT REGISTER IS CONNECTED TO THE DATA INPUT OF THE FIRST FLIP-FLOP OF THE SHIFT REGISTER.
► MOORE MACHINE
► Meally machine
► Johnson counter
► Ring counter
Question No: 23 ( Marks: 1 ) - Please choose one
DRAM STANDS FOR __________
► DYNAMIC RAM
► Data RAM
► Demoduler RAM
► None of given options
Question No: 24 ( Marks: 1 ) - Please choose one
IF THE FIFO MEMORY OUTPUT IS ALREADY FILLED WITH DATA THEN ________
► IT IS LOCKED; NO DATA IS ALLOWED TO ENTER
► IT IS NOT LOCKED; THE NEW DATA OVERWRITES THE PREVIOUS DATA.
► PREVIOUS DATA IS SWAPPED OUT OF MEMORY AND NEW DATA ENTERS
► NONE OF GIVEN OPTIONS
Question No: 25 ( Marks: 1 ) - Please choose one
LUT is acronym for _________
► LOOK UP TABLE
► LOCAL USER TERMINAL
► LEAST UPPER TIME PERIOD
► NONE OF GIVEN OPTIONS
Question No: 26 ( Marks: 1 ) - Please choose one
______ OF A D/A CONVERTER IS DETERMINED BY COMPARING THE ACTUAL OUTPUT OF A D/A CONVERTER WITH THE EXPECTED OUTPUT.
► RESOLUTION
► Accuracy
► Quantization
► Missing Code
Question No: 27 ( Marks: 1 ) - Please choose one
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In the circuit diagram of 3-bit synchronous countershown above, The red rectangle would be replaced which gate?
► AND
► OR
► NAND
► XNOR
Question No: 28 ( Marks: 1 ) - Please choose one
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO _________
► THE FLOP-FLOP IS TRIGGERED
► Q=0 AND Q’=1
► Q=1 AND Q’=0
► THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED
Question No: 29 ( Marks: 1 ) - Please choose one
A FREQUENCY COUNTER ______________
► Counts pulse width
► COUNTS NO. OF CLOCK PULSES IN 1 SECOND
► Counts high and low range of given clock pulse
► NONE OF GIVEN OPTIONS
Question No: 30 ( Marks: 1 ) - Please choose one
Stack is an acronym for _________
► FIFO memory
► LIFO memory
► Flash Memory
► Bust Flash Memory
Question No: 31 ( Marks: 1 )
What is the role of MOS transistor in Mask ROM.
Question No: 32 ( Marks: 1 )
THE GROUP OF BITS 10110111 IS SERIALLY SHIFTED (RIGHT-MOST BIT FIRST) INTO AN 8-BIT PARALLEL OUTPUT SHIFT REGISTER WITH AN INITIAL STATE 11110000. WHAT WILL BE THE CONTENTS OF REGISTER AFTER TWO CLOCK PULSES THE REGISTER CONTAINS?
Question No: 33 ( Marks: 2 )
DRAW THE CIRCUIT DIAGRAM OF GATED S-R LATCH.
Question No: 34 ( Marks: 2 )
HOW MANY BYTES WILL BE THERE IN 32 K X 4 MEMORY?
32 X 1024BYTES X 4 = 131072 BYTES
Question No: 35 ( Marks: 3 )
THE ________ OF FIRST 74HC163 COUNTER IS CONNECTED TO _______ AND ________ INPUTS OF OTHER 74HC COUNTER TO FORM A SINGLE CASCADED COUNTER
Question No: 36 ( Marks: 3 )
GIVEN THE FOLLOWING STATEMENT USED IN PLD PROGRAMMING:
Y PIN 23 ISTYPE ‘COM’;
Explain what does this statement mean?
VARIABLE Y AT OUTPUT PIN 23 WHICH IS A COMBINATIONAL OUTPUT AVAILABLE DIRECTLY FROM THE AND-OR GATE ARRAY OUTPUT.
Y = VARIABLE Y
PIN 23 = PIN NUMBER 23
ISTYPE “COM” = OUTPUT TYPE COMBINATIONAL
Question No: 37 ( Marks: 3 )
WHAT IS MEMORY EXPANSION PROCESS?
Question No: 38 ( Marks: 5 )
CONSIDER THE TABLE GIVEN BELOW, APPLY THE STATE REDUCTION PROCESS ON THE STATES GIVEN IN THE TABLE AND REDUCE THE NUMBER OF STATES AS MUCH AS POSSIBLE.
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Question No: 39 ( Marks: 5 )
PERFORMANCE CHARACTERISTICS OF D/A CONVERTERS ARE DETERMINED BY FIVE PARAMETERS. NAME THEM.
Question No: 40 ( Marks: 10 )
GIVEN BELOW IS THE CIRCUIT DIAGRAM OF BI-DIRECTIONAL 4-BIT SERIAL IN/SERIAL OUT SHIFT REGISTER. REGISTER SHIFTS DATA LEFT OR RIGHT DEPENDS ON THE SIGNAL APPLIED. EXPLAIN HOW THIS CIRCUIT SHIFTS DATA LEFT AND RIGHT.
Question No: 41 ( Marks: 10 )
BRIEFLY EXPLAIN ADDRESS MULTIPLEXING IN DRAM.