CS302- Digital Logic Design final term current paper july 2011

[Vuhelper]

Question No: 1 ( Marks: 1 ) - Please choose one

A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.

► 1

► 2

► 4

► 8





Question No: 2 ( Marks: 1 ) - Please choose one

A frequency counter ______________



► Counts pulse width



► Counts no. of clock pulses in 1 second



► Counts high and low range of given clock pulse



► None of given options



Question No: 3 ( Marks: 1 ) - Please choose one



In a sequential circuit the next state is determined by ________ and _______











► State variable, current state

► Current state, flip-flop output

► Current state and external input

► Input and clock signal applied



Question No: 4 ( Marks: 1 ) - Please choose one

The divide-by-60 counter in digital clock is implemented by using two cascading counters:

► Mod-6, Mod-10

► Mod-50, Mod-10

► Mod-10, Mod-50

► Mod-50, Mod-6





Question No: 5 ( Marks: 1 ) - Please choose one

In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.



► True

► False



Question No: 6 ( Marks: 1 ) - Please choose one

Flip flops are also called _____________

► Bi-stable dualvibrators

► Bi-stable transformer

► Bi-stable multivibrators

► Bi-stable singlevibrators



Question No: 7 ( Marks: 1 ) - Please choose one

The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.



► Set-up time







► Hold time

► Pulse Interval time

► Pulse Stability time (PST)





Question No: 8 ( Marks: 1 ) - Please choose one



74HC163 has two enable input pins which are _______ and _________



► ENP, ENT



► ENI, ENC



► ENP, ENC



► ENT, ENI





Question No: 9 ( Marks: 1 ) - Please choose one

____________ is said to occur when multiple internal variables change due to change in one input variable

► Clock Skew

► Race condition

► Hold delay



► Hold and Wait





Question No: 10 ( Marks: 1 ) - Please choose one

Given the state diagram of an up/down counter, we can find __________





► The next state of a given present state

► The previous state of a given present state

► Both the next and previous states of a given state

► The state diagram shows only the inputs/outputs of a given states



Question No: 11 ( Marks: 1 ) - Please choose one

The _____________ input overrides the ________ input

► Asynchronous, synchronous

► Synchronous, asynchronous

► Preset input (PRE), Clear input (CLR)

► Clear input (CLR), Preset input (PRE)







Question No: 12 ( Marks: 1 ) - Please choose one

A logic circuit with an output consists of ________.





► two AND gates, two OR gates, two inverters

► three AND gates, two OR gates, one inverter

► two AND gates, one OR gate, two inverters

► two AND gates, one OR gate





Question No: 13 ( Marks: 1 ) - Please choose one

A decade counter is __________.

► Mod-3 counter

► Mod-5 counter

► Mod-8 counter



► Mod-10 counter





Question No: 14 ( Marks: 1 ) - Please choose one

In asynchronous transmission when the transmission line is idle, _________





► It is set to logic low

► It is set to logic high

► Remains in previous state

► State of transmission line is not used to start transmission



Question No: 15 ( Marks: 1 ) - Please choose one

A Nibble consists of _____ bits





► 2



► 4

► 8

► 16



Question No: 16 ( Marks: 1 ) - Please choose one

The output of this circuit is always ________.



► 1

► 0

► A

►



Question No: 17 ( Marks: 1 ) - Please choose one

Excess-8 code assigns _______ to “-8”



► 1110

► 1100

► 1000

► 0000





Question No: 18 ( Marks: 1 ) - Please choose one



The voltage gain of the Inverting Amplifier is given by the relation ________





► Vout / Vin = - Rf / Ri

► Vout / Rf = - Vin / Ri

► Rf / Vin = - Ri / Vout

► Rf / Vin = Ri / Vout





Question No: 19 ( Marks: 1 ) - Please choose one

LUT is acronym for _________





► Look Up Table

► Local User Terminal

► Least Upper Time Period

► None of given options



Question No: 20 ( Marks: 1 ) - Please choose one

DRAM stands for __________





► Dynamic RAM

► Data RAM

► Demoduler RAM

► None of given options



Question No: 21 ( Marks: 1 ) - Please choose one

The three fundamental gates are ___________



► AND, NAND, XOR

► OR, AND, NAND

► NOT, NOR, XOR

► NOT, OR, AND









Question No: 22 ( Marks: 1 ) - Please choose one



Which of the following statement is true regarding above block diagram ?

► Triggering takes place on the negative-going edge of the CLK pulse

► Triggering takes place on the positive-going edge of the CLK pulse

► Triggering can take place anytime during the HIGH level of the CLK waveform

► Triggering can take place anytime during the LOW level of the CLK waveform



Question No: 23 ( Marks: 1 ) - Please choose one





The total amount of memory that is supported by any digital system depends upon ______



► The organization of memory

► The structure of memory

► The size of decoding unit

► The size of the address bus of the microprocessor



Question No: 24 ( Marks: 1 ) - Please choose one

The expression F=A+B+C describes the operation of three bits _____ Gate.



► OR

► AND

► NOT

► NAND









Question No: 25 ( Marks: 1 ) - Please choose one

Stack is an acronym for _________



► FIFO memory

► LIFO memory

► Flash Memory

► Bust Flash Memory



Question No: 26 ( Marks: 1 ) - Please choose one

Addition of two octal numbers “36” and “71” results in ________



► 213

► 123

► 127

► 345







Question No: 27 ( Marks: 2 )

Define quantization process.











Question No: 28 ( Marks: 2 )

Explain the difference between 1-to-4 Demultiplexer and 2-to-4 Binary Decoder?





Question No: 29 ( Marks: 2 )



A general Sequential circuit consists of a combinational circuit and a memory element. How this memory element is implemented











Question No: 30 ( Marks: 2 )



Suppose a 2 bit up-counter, having states “A, B, C, D”. Write down GOTO statements to show how present states change to next states.







Question No: 31 ( Marks: 3 )

Name three Operations that can be performed on FLASH Memory





Question No: 32 ( Marks: 3 )

Explain Rotate Right Operation of shift register with the help of diagram.



Question No: 33 ( Marks: 3 )





You are given the block diagram of 74HC190 integrated circuit up/down counter, explain the function of labeled inputs/outputs.





Question No: 34 ( Marks: 5 )

Draw the state diagram of 3-bit up-down counter, use an external input X, when X sets to logic 1, the counter counts downwards, otherwise upward.



Question No: 35 ( Marks: 5 )

Differentiate between synchronous and asynchronous RAM.



Question No: 36 ( Marks: 5 )


Explain Memory Select or Enable Signals