04-24-2011, 07:12 AM
[size=18]full paperz in attachment [/SIZE]
Question No: 1 ( Marks: 1 ) - Please choose one
What is the instruction length of the SRC processor?
► 8 bits
► 16 bits
► 32 bits
► 64 bits
Question No: 2 ( Marks: 1 ) - Please choose one
Which one of the following is the memory organization of FALCON-E processor?
► 28 * 8 bits
► 216 * 8 bits
► 232 * 8 bits
► 264 * 8 bits
Question No: 3 ( Marks: 1 ) - Please choose one
“If P = 1, then load the contents of register R1 into register R2”.
This statement can be written in RTL as:
► R1 ¬ R2
► P: R1 ¬ R2
► P: R2 ¬ R1
► P: R2 ¬ R1, P: R1 ¬ R2
Question No: 4 ( Marks: 1 ) - Please choose one
The instruction ---------------will load the register R3 with the contents of the memory location M [PC+56]
►Add R3, 56
►lar R3, 56
►ldr R3, 56
►str R3, 56
Question No: 5 ( Marks: 1 ) - Please choose one
----------are faster than cache memory
►Accumulator register
►CPU registers
►I/O devices
►ROM
Question No: 6 ( Marks: 1 ) - Please choose one
P: R3 ¬ R5
MAR ¬ IR
These two are instructions written using RTL .If these two operations is to occur simultaneously then which symbol will we use to separate them so that it becomes a correct statement with the condition that two operations occur simultaneously?
► Arrow ¬
► Colon :
► Comma ,
► Parentheses ()
Question No: 7 ( Marks: 1 ) - Please choose one
Prefetching can be considered a primitive form of-------------
►Pipelining
►Multi-processing
►Self-execution
►Exception
Question No: 1 ( Marks: 1 ) - Please choose one
What is the instruction length of the SRC processor?
► 8 bits
► 16 bits
► 32 bits
► 64 bits
Question No: 2 ( Marks: 1 ) - Please choose one
Which one of the following is the memory organization of FALCON-E processor?
► 28 * 8 bits
► 216 * 8 bits
► 232 * 8 bits
► 264 * 8 bits
Question No: 3 ( Marks: 1 ) - Please choose one
“If P = 1, then load the contents of register R1 into register R2”.
This statement can be written in RTL as:
► R1 ¬ R2
► P: R1 ¬ R2
► P: R2 ¬ R1
► P: R2 ¬ R1, P: R1 ¬ R2
Question No: 4 ( Marks: 1 ) - Please choose one
The instruction ---------------will load the register R3 with the contents of the memory location M [PC+56]
►Add R3, 56
►lar R3, 56
►ldr R3, 56
►str R3, 56
Question No: 5 ( Marks: 1 ) - Please choose one
----------are faster than cache memory
►Accumulator register
►CPU registers
►I/O devices
►ROM
Question No: 6 ( Marks: 1 ) - Please choose one
P: R3 ¬ R5
MAR ¬ IR
These two are instructions written using RTL .If these two operations is to occur simultaneously then which symbol will we use to separate them so that it becomes a correct statement with the condition that two operations occur simultaneously?
► Arrow ¬
► Colon :
► Comma ,
► Parentheses ()
Question No: 7 ( Marks: 1 ) - Please choose one
Prefetching can be considered a primitive form of-------------
►Pipelining
►Multi-processing
►Self-execution
►Exception
