Cs501 mid term paper fall december 2011

[Vuhelper]

PAPER#1

1. What is relation b/w data path and control unit in SRC
processors…….2marks
2. Define Pre-fetching……….2marks
3. Write the structural RTL for “ in ra, rb” ……….3marks
4. What is difference between Latency and Throughput……3marks
5. Write the Structural RTL for “call ra, rb”……….5marks
6. What are the pipeline problems. Describe each briefly…. 5marks

PAPER#2

How can you define microprogram? (2 Marks)
A question about to define the shift right instruction? (2 Marks)
What is the utility of reset operation and when it is required? (3
Marks)
Structural RTL instructions definition? (3 Marks)
Write the Structural RTL description for un-conditional jump
instruction for
uni-bus data path implementation. (5 Marks)
Define two hazard in pipelining and how can to overcome these. (5
Marks)

PAPER#3

Q no 1
Define Control unit. (2 marks)
Q no 2
How can you define Microprogram (2 marks)
Q no 3
Instruction fetch say tha yad nahin (3 marks)
rel Ra
Q no 4
what is the utility of reset operation when it is required (3 marks)

Q no5

what are the types of SRC?Name them? also explain its format? (5
marks)

Q no 6
yad nahin muggar uni- bus say related tha (5 marks)

PAPER#4

CS501-Advance Computer Architecture
MID PAPER 18 MAY 2011
BY
SHINING STAR

NOTE:
All MCQS from the file n handouts clear….

1. How many types of instructions are available in SRC? Name them.
What is the format of each of these instructions…….5marks

2. Write the Structural RTL for the call instruction for uni-bus data
path implementation.
call ra, rb…………………..5 marks

3. Write the Structural RTL for the mov instruction for uni-bus data
path implementation.
mov ra, rb………………………..3 marks

4. How many stages are in the pipelined version of SRC? Name
them……..3 marks

5. How can you define microprogram?.....2 marks

6. Write the Structural RTL for the 'not instruction'……….2 marks[B][/B]