12-30-2010, 07:02 PM
Question_1: [marks: 14]
The following serial data are applied to the flip-flop through the AND gates as indicated in figure below. Determine the resulting serial data that appear on the Q output. There is one clock pulse for each bit time. Assume that Q is initially 0 and that and are HIGH.
Rightmost bits are applied first.
J1: 1011110
J2: 0101111
J3: 0111110
K1: 1100110
K2: 0101110
K3: 1101110
Question_2: [marks: 6]
Provide to-the-point (max 4 to 5 lines) answer to the following:
The following serial data are applied to the flip-flop through the AND gates as indicated in figure below. Determine the resulting serial data that appear on the Q output. There is one clock pulse for each bit time. Assume that Q is initially 0 and that and are HIGH.
Rightmost bits are applied first.
J1: 1011110
J2: 0101111
J3: 0111110
K1: 1100110
K2: 0101110
K3: 1101110
Question_2: [marks: 6]
Provide to-the-point (max 4 to 5 lines) answer to the following:
- What is the main difference between a gated S-R latch and an edge-triggered S-R flip-flop?
- How many flip-flops are required to produce a divide-by-32 device?